The present invention relates to ball grid array type semiconductor packages, and more particularly to the design of a trace layout to isolate electrical noise between two adjacent sets of signals in a 2-layer PBGA substrate.
Integrated circuits are typically packaged before they are used with other components as part of a larger electronic system. Ball grid array (BGA) packages are constructed with die mounted on a substrate with bond pads on the die connected to conductive lines or traces on the surface substrate. An array of solder balls mounted on the bottom of the substrate are used to attach the package to a PC board or motherboard, as opposed to molded plastic packages that use lead frames on the outer edges of the package substrate to attach the package to the PC board.
A plastic ball grid array (PBGA) is a wire bond package having a 2-layer organic substrate and solder balls. FIG. 1A is a cross sectional view showing the layer stack-up of a typical 2-layer BGA substrate. The package 10 includes a substrate 12, and a die 14 coupled to signal traces 16 on the top surface of the substrate via wire bonds 22. The substrate 12 typically comprises Bismaleimidie Trizine (BT) or the like. Signal traces 16 on the top layer of the substrate 12 are connected on the bottom of the substrate 12 through vias 18. An array of solder balls 20 are mounted on the bottom of the substrate 12 as well.
Although 2-layer PBGA substrates 12 offer a low cost packaging solution, 2-layer PBGA substrates 12 suffer from electrical noise between adjacent sets of signals and coupling interference.
In order to minimize the electrical noise and the coupling interference, the normal option is to use a more costly enhanced plastic ball grid array (EPBGA). An EPBGA is a wire bond package that uses 4-layer organic substrate for better electrical and thermal performance.
FIG. 1B is a cross sectional view showing the layer stack-up of a typical 4-layer substrate. The substrate 52 comprises a top signal layer 54, ground plane (Vss) layer 56, a power plane (Vdd) layer 58, and a bottom signal layer 60. Signal traces are typically patterned on both the top and bottom signal layers 54 and 60, which are connected to the solder bumps 62 through vias 64. The thicker substrate 52 and the two extra planes 56 and 58 between the top and bottom layers 54 and 60 help reduce noise. However, a 4-layer EPBGA cost 20-30% more than a 2-layer PBGA of a similar design.
Accordingly, what is needed a method for fabricating a semiconductor package to reduce electrical noise between adjacent signals in a 2-layer PBGA without adding additional layers. The present invention addresses such a need.
The present invention provides a method for fabricating a semiconductor package to reduce electrical noise. The semiconductor package uses a 2-layer substrate that includes an array of solder balls on the bottom. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.
According to the system and method disclosed herein, the present invention effectively isolates noise between adjacent signals without adding additional layers and at low cost.